Reading and Writing 1-Wire® Devices Through Serial Interfaces |
Abstract: Thisapplication note presents the electrical aspect of the 1-Wire protocolfor new and legacy devices. A special section explains how to determineappropriate timing parameters for a network comprised of both old andnew 1-Wire slaves. The 1-Wire Master Concepts section providesreferences to other documents that discuss 1-Wire masters in detail andto the related software.Introduction
A 1994 application note explained that the only serial-port interfaceoptions for 1-Wire devices were microcontroller port pins, UARTs, andUART-based COM ports. Since that time special driver chips have beendeveloped for direct connection to a UART, I²C bus, or
USB port. Meanwhile, the number of 1-Wire devices also grew to a long list. (See application note 1796, "
Overview of 1-Wire® Technology and Its Use.")These various developments made it necessary to update the earlierdocumentation. Instead of merging the specifics of all relevantinformation into a single document, this new document refers the readerto other application notes whenever possible.
The Technological Evolution of 1-Wire Devices
The first 1-Wire devices, the DS199x series, were produced in
SRAM technology. Next the
nonvolatileEPROM technology became available, and the DS198x and DS250x seriesdevices were released. These EPROM devices need a 12V programming pulseand are not erasable. The next leap forward was
EEPROMtechnology, which allows programming and erasing at 5V or less. EEPROMtechnology is found in DS197x, DS243x and DS28Exx series devices. Toensure proper power, EEPROM devices may need a master that supports"strong pullup", a feature that temporarily bypasses the 1-Wire pullupresistor with a low-impedance path. The extra power is needed for write
cycles and, in case of the DS1977, also for reading. Besides EEPROM devices, the strong pullup also powers 1-Wire
temperature sensors and special functions such as a SHA-1 engine, which is found in secure 1-Wire devices. Temperature logger
iButtons® use SRAM technology and, therefore, do not have any special, external power requirements.
The 1-Wire Interface
General Information
1-Wire is the only voltage-based digital system that works with two contacts, data and ground, for
half-duplex bidirectional communication. A 1-Wire system consists of a single
1-Wire masterand one or more 1-Wire slaves. The 1-Wire concept relies both on amaster that initiates digital communication, and on self-timed 1-Wireslave devices that synchronize to the master's signal. The timing logicof master and slave must measure and generate digital pulses of variouswidths. When idle, a high-impedance path between the 1-Wire bus and theoperating
voltageputs the 1-Wire bus in the logic-high state. Each device on the busmust be able to pull the 1-Wire bus low at the appropriate time byusing an
open-drainoutput (wired AND). If a transaction needs to be suspended for anyreason, the bus must be left in the idle state so the transaction canresume.
Operating Voltage
Most 1-Wire slave devices operate over the voltage range of 2.8V (min)to 5.25V (max). With few exceptions, 1-Wire devices have no pin forpower supply; they take their energy from the 1-Wire bus (parasiticsupply) or from an embedded battery (some
iButtons). The parasitic supply uses an on-chip capacitor (device specific, 800pF or more) and a
diodein series with a resistor to tap energy from the 1-Wire bus when thebus voltage is higher than the voltage at the capacitor. For the
parasite power supply to function properly, the conditions specified in the 1-Wire device data sheets (i.e., V
PUP, R
PUP, t
REC)must be met. The recovery time values apply to a network with oneslave. For multiple-slave networks, the recovery time needs to beextended; alternatively one could lower the pullup resistor value orchange to a 1-Wire master with active pullup. For further reading onthis matter refer to application note 3829, "
Determining the Recovery Time for Multiple-Slave 1-Wire Networks."
Extra Energy
Usually, the parasitic supply provides enough energy for communication,i.e., addressing and reading from a 1-Wire device as well as writing toSRAM-based devices. Additional energy is required for writing toEEPROMs, reading the DS1977 32KB EEPROM
iButton,and using special functions such as temperature converters or running aSHA-1 engine. This energy is to be delivered at certain times in theprotocol when the 1-Wire bus is idle. Application note 4255, "
How to Power the Extended Features of 1-Wire® Devices," lists these devices and describes different ways to ensure proper power delivery.
1-Wire Speeds
Early 1-Wire devices and UART-based master circuits communicated at aspeed of up to 16.3kbps, which is now called "standard speed." Toreduce the time needed to read a 64Kbit memory
iButtonto less than 1 second, a high-speed mode called "overdrive" was added.Almost all 1-Wire devices developed in recent years support overdrive.
1-Wire Timing
Data sheets descriptions of 1-Wire timing havechanged over time. Most 1-Wire data-sheet descriptions fall into twocategories: legacy style (the vast majority), and new style.
The new-style timing description distinguishes between the perspectiveof the master and the slave. This approach was introduced inconjunction with a new 1-Wire front-end. (See application note 3925, "
1-Wire Extended Network Standard.")The new style specifies master's requirements as a result of slaveperformance, and also takes into account the impact of rise and falltimes on the 1-Wire bus. The legacy style of description places moreemphasis on the slave's performance, which occasionally has beenmisinterpreted. Both descriptive styles use slightly different namesfor the same parameter (
Table 1); not all parameters of onestyle have a direct match in the other style. In the new style, therecovery time is included in the length of a time slot; in the legacystyle, the recovery time is not included. Besides these two styles,some data sheets in the DS27xx and DS18xx series use a less-detailedvariant of the legacy style. Data sheets of the DS1921 series adaptedthe new style to parts that do not have the new 1-Wire front-end.
The following sections review the timing description in both styles.
Table 1. Parameters that Describe the 1-Wire Interface | Symbol | Description |
| New Style | Legacy Style |
| RPUP | — | Pullup resistor (value not specified in legacy style) |
| VPUP | VPULLUP | 1-Wire pullup voltage |
| — | VPULLUP MIN | Minimum permissible pullup voltage |
| — | VIH MIN | Minimum slave-input high voltage |
| VILMAX | VIL MAX | Slave's maximum-input low voltage |
| VIHMASTER | — | Minimum master-input high voltage |
| VTL | — | Slave's falling-edge switching threshold (new front-end) |
| VTH | — | Slave's rising-edge switching threshold (new front-end) |
| VHY | — | Slave's rising-edge switching hysteresis (new front-end) |
| tF | — | Duration of the falling edge of a master-initiated 1-Wire activity |
| tRSTL | tRSTL | Reset low time |
| ε | — | Duration of the rising edge on the 1-Wire bus from 0V to VTH (new front-end) |
| — | tR | Duration of the rising edge on the 1-Wire bus from VIL MAX to VIH MIN |
| tPDH | tPDH | Presence-detect high time |
| tPDL | tPDL | Presence-detect low time |
| tFPD | — | Presence-pulse fall time (some devices with new front-end) |
| tMSP | — | Presence-detect sample time, derived from slave performance |
| tREH | — | Rising-edge hold-off time (new front-end) |
| — | tRSTH | Reset high time (N/A for the new front-end) |
| tW1L | tLOW1 | Write-one low time |
| tW0L | tLOW0 | Write-zero low time |
| tREC | tREC | Recovery time |
| tRL | tLOWR | Read low time, derived from slave performance |
| — | tSU | Read data setup time |
| — | tRDV | Minimum time for which data is valid in a read data time slot |
| — | tRELEASE | Additional time for which data could be valid in a read data time slot |
| tMSR | — | Read sample time, derived from slave performance |
| δ | — | Duration of the rising edge on the 1-Wire bus from 0V to VIHMASTER |
| tSLOT | tSLOT | Legacy style: time to communicate one bit excluding recovery time;
New style: time to communicate one bit including recovery time |
New-Style Timing Description
Reset and Presence Detect
1-Wire communication begins with a reset-/presence-detect cycle (
Figure 1). To get from idle to active, the voltage on the 1-Wire bus must fall from V
PUP below the threshold, V
TL. To get from active to idle, the voltage needs to rise from V
ILMAX past the threshold, V
TH.The time it takes for the voltage to make this rise is seen in Figure 1as "ε," and its duration depends both on the pullup resistor, R
PUP, used and the capacitance of the 1-Wire network attached. The voltage V
ILMAX is relevant for the slave when determining a logical level, not for triggering any events.
If the master uses slew-rate control on the falling edge, the master must pull down the line for t
RSTL + t
F to compensate for the edge. A t
RSTLduration of 480µs or longer exits the Overdrive Mode, returning thedevice to standard speed. If a slave is in Overdrive Mode and t
RSTL is no longer than 80µs, the device remains in Overdrive Mode. If a slave is in Overdrive Mode and t
RSTL is
between 80µs and 480µs, the device will reset but the communication speed is undetermined.
After the bus master has released the line, it goes into receive mode. Now the 1-Wire bus is pulled to V
PUP through the pullup resistor. When the threshold, V
TH, is crossed, the slave waits for t
PDH and then transmits a presence pulse by pulling the line low for t
PDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at t
MSP. The t
RSTH window must be at least the sum of t
PDHMAX, t
PDLMAX, and t
RECMIN. Immediately after t
RSTH is expired, a slave with the new front-end is ready for data communication.
Figure 1. Reset and presence pulse.Read/Write Time Slots
After the reset-/presence-detect cycle is completed, a 1-Wire slave isready for communication using time slots. Each time slot carries asingle bit. Write time slots transport data from the bus master to aslave. Read time slots
transfer data from a slave to the master.
Figure 2 illustrates the definitions of the write and read time slots.
A time slot begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold, V
TL,a slave starts its internal timing generator, which determines when thedata line is sampled during a write time slot and how long data isvalid during a read time slot.
Master-to-Slave
For a
write-one time slot, the voltage on the data line must have crossed the V
TH threshold before the write-one low time, t
W1LMAX, is expired. For a
write-zero time slot, the voltage on the data line must stay below the V
TH threshold until the write-zero low time, t
W0LMIN, is expired. After the V
TH threshold has been crossed, a slave needs a recovery time, t
REC, before it is ready for the next time slot.
Figure 2. Read/write timing diagram.Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V
TL until the read-low time, t
RL, is expired. During the t
RLwindow, when responding with a 0, a slave starts pulling the data linelow; its internal timing generator determines when this pulldown endsand the voltage starts rising again. When responding with a 1, a slavedoes not hold the data line low, and the voltage starts rising as soonas t
RL is over. The sum of t
RL + δ (rise time) onone side and the internal timing generator of the slave on the otherside define the master sampling window, t
MSRMIN to t
MSRMAX, in which the master must perform a read from the data line. After reading from the data line, the master must wait until t
SLOT is expired.
Improved Network Behavior
In a 1-Wire environment, line termination is possible only duringtransients controlled by the bus master (1-Wire driver). 1-Wirenetworks, therefore, are susceptible to noise from various origins.Depending on the physical size and topology of the network, reflectionsfrom end points and branch points can add up, or cancel each other tosome extent. Such reflections are visible as glitches or ringing on the1-Wire communication line. Noise coupled onto the 1-Wire line fromexternal sources can also result in signal glitching. A
glitchduring the rising edge of a time slot can cause a slave device to losesynchronization with the master and, consequently, result in a searchROM command coming to a dead end or cause a device-specific functioncommand to abort.
To achieve better performance in network applications, the new 1-Wirefront-end was developed, which is less sensitive to noise. This new1-Wire front-end implements the first two, or more, of the followingfeatures. Device data sheets use the parameters t
REH and t
FPD to indicate whether features 3 and 4 are implemented.
- There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. This additional filtering does not apply at overdrive speed.
- There is a hysteresis at the low-to-high switching threshold, VTH. If a negative glitch crosses VTH but does not go below VTH - VHY, it will not be recognized (Figure 3a). The hysteresis is effective at any 1-Wire speed.
- (Optional) There is a time window specified by the rising-edge hold-off time, tREH, during which glitches are ignored, even if they extend below the VTH - VHY threshold (Figure 3b, tGL < tREH). Deep voltage droops or glitches that appear late after crossing the VTH threshold and extend beyond the tREH window cannot be filtered out; they are understood as the beginning of a new time slot (Figure 3c, tGL ≥ tREH).
- (Optional) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line impedance than a digitally switched transistor. It converts the high-frequency ringing found in traditional devices into a smoother low-bandwidth transition. The slew-rate control is specified by the parameter tFPD, which has different values for standard and overdrive speed.
The new 1-Wire front-end is also referred to as the 1-Wire Extended Network Standard. Application note 3925 (see above under
1-Wire Timing)shows the differences in the timing specifications compared to earlier1-Wire devices, and includes a table of devices that have the newfront-end.
Legacy Style Description
Reset and Presence Detect
The reset pulse provides a clear starting condition that supersedes anytime-slot synchronization. The reset pulse is defined as a single lowpulse with a duration of t
RSTL followed by a reset-high time, t
RSTH (
Figure 4). After a reset pulse has been sent, the 1-Wire device waits for the time t
PDH and then generates a presence pulse of duration t
PDL. No other communication on the 1-Wire bus is allowed during t
RSTH.
Figure 4. Legacy reset and presence pulse.Read/Write Time Slots
Commands and data are sent to 1-Wire devices by combining write-one and write-zero time slots (
Figure 5). To read data, the master has to generate read-data time slots to define the start condition of each bit.
Master-to-Slave
The duration of a low pulse to write a 1 is t
LOW1. To write a 0, the duration of the low pulse is t
LOW0. At the end of the active part of each time slot, 1-Wire devices need a recovery time, t
REC,to prepare for the next bit. This recovery time is the inactive part ofa time slot, since it must be added to the duration of the active partto obtain the time it takes to transfer one bit.
Slave-to-Master
The read-data time slot looks essentially the same as the write-1 timeslot from the master's point of view. Starting at the high-to-lowtransition, the slave sends a single bit of its addressed contents. Ifthe data bit is a 1, the slave leaves the pulse unchanged. If the databit is a 0, the slave pulls the data line low for t
RDV (Figure 5). In this time frame the data is valid for reading by the master. Following t
RDV there is an additional time interval, t
RELEASE, after which the slave releases the 1-Wire line so that its voltage can return to V
PULLUP.
Figure 5. Legacy read/write timing diagram.Mixing New Front-End Parts with Legacy Parts
1-Wire devices with new and legacy front-ends can share the same 1-Wirebus. Since the parameters describing the 1-Wire timing for the new andthe old front-end differ somewhat, it is not obvious how to determine acompatible set of timing parameters for the master.
Table 2 recommends how to accomplish this task. When using the spreadsheet of application note 126, "
1-Wire® Communication Through Software,"these parameters are required as input to calculate the duration ofvarious segments that implement 1-Wire communications. Since the morerecent application notes use the terminology of the new front-end,Table 2 is also helpful when working with self-timed 1-Wire mastersthat connect to a UART, I²C bus, or USB port.
Table 2. Determining 1-Wire Timing Parameters in a Mixed Network | tW1L | Select the value specified for the slave(s) with the new front-end that is also within the permissible range of the slave(s) with the old front-end. |
| tSLOT | Use the value required by the slave(s) with the new front-end. |
| tW0L | Select the value specified for the slave(s) with the new front-end that is also within the permissible range of the slave(s) with the old front-end. |
| tREC | Use the value specified for the slave(s) with the new front-end. |
| tRL | Select a value that is close to the minimum value specified for the slave(s) with the new front-end. |
| tMSR | Select a value that does not exceed tRDV and that does not violate the maximum tMSR specification of the slave(s) with the new front-end. |
| tRSTL | Select a value that is in the permissible range for both types of devices. |
| tMSP | Calculate the value that applies to the slave(s) with the legacy front-end: tMSPMIN = tPDHmax. tMSPMAX = tPDHmin + tPDLmin. Compare the calculation result to the tMSP specification of the slaves with the new front-end, and choose a value that works for all slaves. If a slave with the new front-end has slew-rate control on the presence pulse (i.e., parameter tFPD specified), it is possible that no common value can be found. In that case separate 1-Wire busses are necessary. |
| tRSTH | Use the value required by the slave(s) with the legacy front-end. |
1-Wire Master Concepts
Earlier documentation presented two types of master interfaces, nowcalled "port pin attachments" and "UART attachments". Special chipshave since been developed, which add the new types of master interfacescalled "I²C bus attachments" and "USB attachments". Software developedfaster than hardware. The most comprehensive document on 1-Wiresoftware is Application note 155, "
1-Wire® Software Resource Guide Device Description,"which refers to various application program interfaces (APIs). All ofthe APIs described in application note 155 are free to use withoutrestriction and, in most cases, include the complete source code.
Port Pin Attachments
The common characteristic of this master interface is the use of one or more port pins from a microcontroller or a
FPGA. These pins can be "general purpose" or dedicated (See sections titled
Microcontroller with Built-In 1-Wire Master and
Synthesizable 1-Wire Bus Master in application note 4206, "
Choosing the Right 1-Wire® Master for Embedded Applications").This type of interface is discussed in categories 1, 2, and 3 inapplication note 4206. Port pin attachments can work for standard speedand overdrive speed.
UART Attachments
There are two ways to create 1-Wire communication through a UART. Thetraditional way uses the timing capabilities of the UART directly, buthas to invest one character to generate one time slot or thereset-/presence-detect sequence. This concept is described inapplication note 214, "
Using a UART to Implement a 1-Wire Bus Master."Although efficient under operating systems such as DOS, modernoperating systems make the access to UART registers quite inefficient.For this reason, this type of UART attachment is no longer popular for1-Wire applications.
The new UART attachment uses a special protocol converter chip, theDS2480B, to generate 1-Wire communication. This device increases theefficiency (one character for 8 time slots) and allows 1-Wire overdrivespeed. This type of interface is discussed in category 4,
Serial Interface Protocol Conversions, of application note 4206 (see above). If properly configured (see application note 4104, "
Understanding and Configuring the 1-Wire Timing of the DS2480B"),the DS2480B can drive more than 30 slaves in standard speed and atleast nine in overdrive speed. The DS2480B is the only integrated1-Wire master that can program EPROM devices.
I²C Bus Attachments
Most modern microcontrollers include an I²C bus master port. Althoughsharing some common characteristics (half-duplex communication andbidirectional data pin), 1-Wire devices cannot be connected to an I²Cbus without a bridge. Maxim has developed three bridge chips, theDS2482-100, DS2482-101 and DS2482-800. The first two devices have asingle 1-Wire master port; the other chip drives up to eight 1-Wirenetworks. Although not as strong as the DS2480B, these parts are wellsuited for embedded applications. The I²C to 1-Wire bridge is discussedin category 4, Serial Interface Protocol Conversions, of applicationnote 4206.
USB Attachments
USB ports are commonly found on PCs and portable electronics, andreplace the traditional UART-based COM port. To provide 1-Wireconnectivity to USB ports, Maxim has developed the DS2490 USB to 1-Wirebridge chip. Although not as strong as the DS2480B, the DS2490 candrive a 1-Wire bus with several slaves. The USB to 1-Wire bridge isdiscussed in category 4, Serial Interface Protocol Conversions, ofapplication note 4206.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
iButton is a registered trademark of Maxim Integrated Products, Inc.
