本公众号【读芯树:duxinshu_PD】主要介绍数字集成电路物理设计相关知识,才疏学浅,如有错误,欢迎指正交流学习。
这是集成电路物理设计的第三个系列【File】的第四篇文章,本篇文章主要讲解SPEF file相关内容:
1,什么是SPEF fille?
SPEF = standard parasitic exchange format
每一条net都会存在电阻和寄生电容,这些信息保存在SPEF文件中。
SPEF文件是一种标准的中间文件,可以应用于不同的EDA工具。
在STA分析时,需要SPEF文件进行cell/net delay的计算。
在IR分析时,需要SPEF文件得到net的RC信息。
SPEF文件一般是通过starrc或者qrc得到。
2,SPEF File介绍
Header Section
Parasitic Extraction Tool Name
Name Map Section
Top Level Port Section
port的方向有I: input, O: output, B: inout
Parasitic description Section
*D_NET: the net mapping name, sum of all capacitance。*I: internal pins [*I <pin name> <direction> *C <xy coordinate> <loading or driving information>] (*C: gives the xy coordinate of pin in layout, *L: gives the load capacitance for an input pin, *D: gives the driving cell type for an output pin)。*CAP section:net上所有的电容信息,主要包括两部分:对地电容和耦合电容。(capacitor lumped to ground包括三部分:an identifying number, a node name,the capacitance value of the node;coupling capacitor包括四部分:an identifying number, two nodes name, the capacitance value between the node。)*RES section:net上所有的电阻信息。(resistor包括四部分:an identifying numbers, two nodes name, the value of resistance between two nodes。)
3,SPF/SPEF/DSPF/RSPF的区别
SPF = standard parasitic format (a Cadence Design System standard for defining netlist parasitic)
SPEF = standard parasitic exchange format (an Open Verilog Initiative and IEEE format)
DSPF = detailed standard parasitic format (detailed network of RC parasitic)
RSPF = reduced standard parasitic format (each net as an RC 'PI' model)
4,SPEF Flow
StarRC Flow:
>TOP_DEF_FILE: ./design.def>MAPPING_FILE ./starrc.map>NETLIST_FILE: ./design.spef.gz>NETLIST_COMPRESS_COMMAND: gzip -q -f>HIERARCHICAL_SEPARATOR: />METAL_FILL_GDS_FILE: ./design.dummy_metal.gds.gz>MMETAL_FILL_GDS_BLOCK: DM_design>GDS_LAYER_MAP_FILE: mapping_map>METAL_FILL_POLYGON_HANDLING: FLOATING>DENSITY_BASED_THICKNESS: YES>METAL_FILL_POLYGON_HANDLING: FLOATING>COUPLING_ABS_THRESHOLD: 5E-16>COUPLING_REL_THRESHOLD: 0.03>REDUCTION: NO_EXTRA_LOOPS>CORNERS_FILE: ./corner.smcTCAD_GRD_FILE: ./typical.nxtgrdOPERATING_TEMPERATURE: 70)>SIMULATANEOOUS_MULTI_CORNER: YES>SELECTED_CORNERS: typical_70
QRC Flow:
>distribured_processing -multi_cpu 16>input_db -type def -design_file ./design.def.gz -lef_file_list cell.lef>>input_db -type metal_fill -gds_file ./design.dummy_metal.gds.gz>extraction_setup -stream_layer_map M1 3300 151 fill 1 ...>graybox -type lef_obstruction>process_technology -technology_library_file ./techfile -technology_name N16 -technology_corner typical -temperature 70>capacitance -decoupling_factor 1.0 -mode high>extraction_setup -max_fracture_length 25 -enable_dpt_corlor_import true -technology_layer_map M1 M1 ...>extracct -selection all -type rc_coupled>hierarchical_extract -hierarchical_cell_list_file ./macros.cellllist>parasitic_reduction -enable_reduction false>extract -selection 'net *VDD*' -type none>extract -selection 'net *VSS*' -type none>metal_fill -type 'floating'>output_setup -compressed true -enable_short_check all -write_incomplete_shorts_nets_file true>output_db -type spef -hierarchy_delimiter '/' -output_incomplete_nets true -output_unrouted_nets true -subtype 'standard'> filter_coupling_cap -cap_filtering_mode absolute_and_relative -total_cap_threshold 0 -coupling_cap_threshold_absolute 0.1 -coupling_cap_threshold_relative 1>output_setup -file_name design.spef -directory_name ../spef/ -file_max_size 200000000>log_file -dum_option true -max_warning_messages 100 -file_name ./log/qrc.log>log_file -strict_error_report true -abort_upon_missing_macro true
1,Fusion Compiler/ IC Compiler 2 user guide
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