Arm GPU Mali-T820/T830和 Mail-G51性能比较

以下内容官网直翻，没有修改：

The Arm Mali-T820 GPU and Arm Mali-T830 GPU provide a staggered approach to performance, providing significant improvements over previous generations. The Mali-T830 GPU has more compute capability per shader core and handles more complex content than the Mali-T820 GPU. The Mali-T820 GPU and Mali-T830 GPU are the first mainstream Mali GPUs to introduce OpenGL ES 3.2 API support, Android Extension pack support and Arm Framebuffer Compression support.

ARM马里-T820GPU和ARM马里-T830GPU提供了一种交错的性能方法，提供了比前几代显著的改进。与马里-t820 GPU相比，马里-T830 GPU具有更高的每个着色器内核的计算能力，并处理更复杂的内容。马里-t820 GPU和马里-T830 GPU是首批引入OpenGL ES 3.2 API支持、Android扩展包支持和ARM Framebuffer压缩支持的主流马里GPU。

The Arm Mali-G51 high area efficiency GPU was the first GPU to take the Bifrost graphics architecture to mainstream devices. Focused on efficiency, the Mali-G51 provides best ever energy efficiency, and improves area efficiency and performance density over the previous generation of devices. Mali-G51 is also the smallest Vulkan enabled GPU and brings complex content such as Virtual Spaces and 360 video to the mainstream market. 

ARM马里-G51高区域效率GPU是第一个将Bifrost图形架构应用于主流设备的GPU。马里-G51专注于效率，提供有史以来最好的能源效率，与前一代设备相比，提高了区域效率和性能密度。马里-G51也是最小的支持Vulkan的GPU，并将虚拟空间和360视频等复杂内容引入主流市场。

Mali-T820/T830构架

Mail-G51 构架

两者构架分别是Midgard和Bifrost, 有很大差别。G51的核心数不能够通过后面的“MPx”来判断，其判断方法如下图。

详细参数对比：

	Mali-T820/T830 Midgard graphics architecture		Mali-G51 Bifrost graphics architecture
Features	Value	Description	Value	Description
Anti-Aliasing	4x MSAA.	4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop.	4x MSAA	4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop.
			8x MSAA
			16x MSAA
API Support	OpenGL® ES 1.1, 2.0, 3.1, 3.2.	Support for a wide range of graphics APIs.	OpenGL® ES 1.1, 2.0, 3.1, 3.2	Full support for next-generation and legacy 2D/3D graphics applications.
	Vulkan 1.0		Vulkan 1.0*
	OpenCL® 1.1, 1.2 Full Profile.		OpenCL® 1.1, 1.2, 2.0 Full Profile,
	RenderScript.		RenderScript
Bus Interface	AMBA®4.	Compatible with a wide range of bus interconnect and peripheral IP.	AMBA®4	Compatible with a wide range of bus interconnect and peripheral IP.
	ACE-Lite.		ACE-LITE
L2 Cache	Configurable 32KB-256KB.	64KB-128KB for MP1 & MP2.	Configurable 32kB-512kB	32KB-64KB for MP1.
				64KB-128KB for MP2.
		64KB-256KB for MP3.		128KB-256KB for MP3 & MP4.
		128KB-256KB for MP4.		256KB-512KB for MP6 configurations.
Memory System	Virtual Memory.	Built-in Memory Management Unit (MMU) to support virtual memory.	Virtual Memory	Built-in Memory Management Unit (MMU) to support virtual memory.
Multi-Core Scaling	1 to 4 cores.	Optimized for high area and energy efficiency to address mainstream device requirements.	1 uni-pixel core to 3 dual-pixel cores	Optimized for high area and energy efficiency to address mainstream device requirements.
Adaptive Scalable Texture Compression (ASTC)	Low Dynamic Range (LDR) and High Dynamic Range (HDR).	ASTC offers a number of advantages over existing texture compression schemes by improving image quality, reducing memory bandwidth and thus energy use.	Low dynamic range (LDR) and high dynamic range (HDR).	ASTC offers a number of advantages over existing texture compression schemes by improving image quality, reducing memory bandwidth and thus energy use.
Arm Frame Buffer Compression (AFBC)	4x4 pixel block size.	AFBC is a lossless image compression format that provides random access to pixel data to a 4x4 pixel block granularity. It is employed to reduce memory bandwidth both internally within the GPU and externally throughout the SoC.	Version 1.2 4x4 pixel block size	AFBC is a lossless image compression format that provides random access to pixel data to a 4x4 pixel block granularity. It is employed to reduce memory bandwidth both internally within the GPU and externally throughout the SoC.
Transaction Elimination	16x16 pixel block size.	Transaction Elimination locates identical pixel blocks from two consecutive render targets and performs a partial update to the frame buffer with the changed pixel blocks only, which reduces memory bandwidth and thus energy.	16x16 pixel block size	Transaction Elimination spots the identical pixel blocks between two consecutive render targets and performs a partial update to the frame buffer with the changed pixel blocks only, which reduces memory bandwidth and thus energy.
Smart Composition	16x16 pixel block size.	Smart Composition extends the concept of Transaction Elimination to every stage of UI composition. Identical pixel blocks of input surfaces are not read, not processed for composition and not written to final frame buffer.	16x16 pixel block size	Smart Composition extends the concept of Transaction Elimination to every stage of UI composition. Identical pixel blocks of input surfaces are not read, not processed for composition and not written to final frame buffer.