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Home > System Control Coprocessor > System control coprocessor registers > c1, Control Register |
The purpose of the Control Register is to provide control and configuration of:
memory alignment, endianness, protection, and fault behavior
MMU, cache enables, and cache replacement strategy
interrupts and behavior of interrupt latency
location for exception vectors
program flow prediction.
The Control Register is:
a 32-bit read/write register
accessible in privileged modes only
partially banked.
Figure 3.20 shows the bit arrangement of the Control Register.
Table 3.46 shows how the bit values correspond with the Control Register functions.
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