异步置数（低有效）的10进制计数器

 

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

 

ENTITY counter10 IS

    PORT( clk: IN STD_LOGIC;

             load: IN STD_LOGIC;

               din: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

             qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

                  c: OUT STD_LOGIC);

END counter10;

 

ARCHITECTURE art OF counter10 IS

    SIGNAL temp: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

     PROCESS(clk,load,din)

     BEGIN

         IF(load='0') THEN

              temp<=din;

         ELSIF(clk'EVENT AND clk='1') THEN

              IF(temp="1001") THEN

                    temp<="0000";

              ELSE

                    temp<=temp+1;

              END IF;

         END IF;

    END PROCESS;

    qout<=temp;

    c<='1' WHEN temp="1001" ELSE

         '0';

END art;